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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">cy_stc_syspm_backup_regs_t Struct Reference<div class="ingroups"><a class="el" href="group__group__syspm.html">SysPm        (System Power Management)</a> &raquo; <a class="el" href="group__group__syspm__data__structures.html">Data Structures</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>This internal structure stores non-retained registers in the system Deep Sleep power mode. </p>
<dl class="section note"><dt>Note</dt><dd>This enum is available for CAT1A devices. On wakeup from system Deep Sleep, these registers are restored. </dd></dl>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a6bc5a15177c3023affabce875d1eeb0b"><td class="memItemLeft" align="right" valign="top"><a id="a6bc5a15177c3023affabce875d1eeb0b"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__syspm__backup__regs__t.html#a6bc5a15177c3023affabce875d1eeb0b">CY_SYSPM_UDB_UDBIF_BANK_CTL_REG</a></td></tr>
<tr class="memdesc:a6bc5a15177c3023affabce875d1eeb0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">UDB interface control register. <br /></td></tr>
<tr class="separator:a6bc5a15177c3023affabce875d1eeb0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4f58edd2bbb9f9d7438f7dd692b20c77"><td class="memItemLeft" align="right" valign="top"><a id="a4f58edd2bbb9f9d7438f7dd692b20c77"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__syspm__backup__regs__t.html#a4f58edd2bbb9f9d7438f7dd692b20c77">CY_SYSPM_UDB_BCTL_MDCLK_EN_REG</a></td></tr>
<tr class="memdesc:a4f58edd2bbb9f9d7438f7dd692b20c77"><td class="mdescLeft">&#160;</td><td class="mdescRight">UDB bank MDCLK_EN register. <br /></td></tr>
<tr class="separator:a4f58edd2bbb9f9d7438f7dd692b20c77"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:affbf261511d88b2991832a4b86b3d30d"><td class="memItemLeft" align="right" valign="top"><a id="affbf261511d88b2991832a4b86b3d30d"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__syspm__backup__regs__t.html#affbf261511d88b2991832a4b86b3d30d">CY_SYSPM_UDB_BCTL_MBCLK_EN_REG</a></td></tr>
<tr class="memdesc:affbf261511d88b2991832a4b86b3d30d"><td class="mdescLeft">&#160;</td><td class="mdescRight">UDB bank MBCLK_EN register. <br /></td></tr>
<tr class="separator:affbf261511d88b2991832a4b86b3d30d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7d21a7fc1a0698e3b6ccd239bf0f61d7"><td class="memItemLeft" align="right" valign="top"><a id="a7d21a7fc1a0698e3b6ccd239bf0f61d7"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__syspm__backup__regs__t.html#a7d21a7fc1a0698e3b6ccd239bf0f61d7">CY_SYSPM_UDB_BCTL_BOTSEL_L_REG</a></td></tr>
<tr class="memdesc:a7d21a7fc1a0698e3b6ccd239bf0f61d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">UDB bank BOTSEL_L register. <br /></td></tr>
<tr class="separator:a7d21a7fc1a0698e3b6ccd239bf0f61d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a04be592ea14d7b5e84bb8d92739fb8cb"><td class="memItemLeft" align="right" valign="top"><a id="a04be592ea14d7b5e84bb8d92739fb8cb"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__syspm__backup__regs__t.html#a04be592ea14d7b5e84bb8d92739fb8cb">CY_SYSPM_UDB_BCTL_BOTSEL_U_REG</a></td></tr>
<tr class="memdesc:a04be592ea14d7b5e84bb8d92739fb8cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">UDB bank BOTSEL_U register. <br /></td></tr>
<tr class="separator:a04be592ea14d7b5e84bb8d92739fb8cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5068cbfd2936c39e7e7724378f266016"><td class="memItemLeft" align="right" valign="top"><a id="a5068cbfd2936c39e7e7724378f266016"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__syspm__backup__regs__t.html#a5068cbfd2936c39e7e7724378f266016">CY_SYSPM_UDB_BCTL_QCLK_EN0_REG</a></td></tr>
<tr class="memdesc:a5068cbfd2936c39e7e7724378f266016"><td class="mdescLeft">&#160;</td><td class="mdescRight">UDB bank QCLK_EN0 register. <br /></td></tr>
<tr class="separator:a5068cbfd2936c39e7e7724378f266016"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8cc818e75611888adf64f5e0b20a3434"><td class="memItemLeft" align="right" valign="top"><a id="a8cc818e75611888adf64f5e0b20a3434"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__syspm__backup__regs__t.html#a8cc818e75611888adf64f5e0b20a3434">CY_SYSPM_UDB_BCTL_QCLK_EN1_REG</a></td></tr>
<tr class="memdesc:a8cc818e75611888adf64f5e0b20a3434"><td class="mdescLeft">&#160;</td><td class="mdescRight">UDB bank QCLK_EN1 register. <br /></td></tr>
<tr class="separator:a8cc818e75611888adf64f5e0b20a3434"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a65d069c377b68b7d08385fcf58bfa05b"><td class="memItemLeft" align="right" valign="top"><a id="a65d069c377b68b7d08385fcf58bfa05b"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__syspm__backup__regs__t.html#a65d069c377b68b7d08385fcf58bfa05b">CY_SYSPM_UDB_BCTL_QCLK_EN2_REG</a></td></tr>
<tr class="memdesc:a65d069c377b68b7d08385fcf58bfa05b"><td class="mdescLeft">&#160;</td><td class="mdescRight">UDB bank QCLK_EN2 register. <br /></td></tr>
<tr class="separator:a65d069c377b68b7d08385fcf58bfa05b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a02e66f69904911561a3143bbcff5627f"><td class="memItemLeft" align="right" valign="top"><a id="a02e66f69904911561a3143bbcff5627f"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__syspm__backup__regs__t.html#a02e66f69904911561a3143bbcff5627f">CY_SYSPM_CM0_CLOCK_CTL_REG</a></td></tr>
<tr class="memdesc:a02e66f69904911561a3143bbcff5627f"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPUSS CM0+ clock control register. <br /></td></tr>
<tr class="separator:a02e66f69904911561a3143bbcff5627f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af4a272d28fb71f4f52b1eae964256d09"><td class="memItemLeft" align="right" valign="top"><a id="af4a272d28fb71f4f52b1eae964256d09"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__syspm__backup__regs__t.html#af4a272d28fb71f4f52b1eae964256d09">CY_SYSPM_CM4_CLOCK_CTL_REG</a></td></tr>
<tr class="memdesc:af4a272d28fb71f4f52b1eae964256d09"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPUSS CM4 clock control register. <br /></td></tr>
<tr class="separator:af4a272d28fb71f4f52b1eae964256d09"><td class="memSeparator" colspan="2">&#160;</td></tr>
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